Non-equilibrium Thermal Effects in Power Transistors

This work addresses electro-thermal simulation of LDMOS devices and associated non-equilibrium effects. Simulations have been performed on three kinds of LDMOS i.e. bulk Si, partial SOI and SOI, with a view to compare the extent of non-equilibrium in each. Phonon temperature contours and electron energies were analyzed in each case. The results indicate that, under similar operating conditions, non-equilibrium is most pronounced in case of SOI devices. A comparison between transient and steady state acoustic phonon temperatures indicates that the mechanisms and device regions associated with nonequilibrium could be very different depending on the switching rate. Analysis of the effective mean free path of carriers in the active region shows that the primary source of heat generation is carrier-phonon scattering and not Joule heating as is generally assumed. Under steady state conditions however, device heating due to these two mechanisms looks very similar. NOMENCLATURE C bulk thermal capacitance of Si Ca acoustic phonon thermal capacitance Co optical phonon thermal capacitance D thermal diffusivity G generation rate of holes or electrons H generation term in bulk conduction equation J current density k bulk thermal conductivity of Si ka thermal conductivity of acoustic phonons kb Boltzmann constant Lg gate length m effective mass ND doping concentration q electron charge Ta acoustic phonon temperature To optical phonon temperature TL lattice temperature S energy flux V voltage v carrier velocity W energy density loss rate ε local permittivity μ mobility η carrier density κ electron thermal conductivity ψ electrostatic potential * Address all correspondence to this author e-mail : [email protected] ρ local space charge density τe-L electron-lattice scattering time constant INTRODUCTION MOSFETs are widely used in a variety of power systems because of certain inherent characteristics. In high speed switching applications these devices offer low on-state resistance [1]. In high frequency RF applications they exhibit low capacitance and high gain (LDMOS) or high stability (VDMOS) [2]. MOS can also be integrated with signal processing circuits to form ‘smart chips’ and IPLSIs [3]. The present work focuses on LDMOS, which is better suited for high frequency applications such as telecommunication circuits. These lateral surface effect devices are however, susceptible to hot carrier currents that induce several breakdown mechanisms. Various efforts have been directed towards characterizing hot carrier effects in LDMOS, and suggestions have been made to mitigate such effects [4]-[6]. These attempts represent a modest improvement in thermal management, and the devices are still likely to exhibit thermal problems. It is for this reason that thermal simulations of LDMOS are crucial for accurate estimates of device performance. Numerical simulations are widely used to understand device physics and predict non-equilibrium behavior in sub-micron devices, because the length and time scales involved are not easily amenable to experimental analysis. It is thus imperative that the simulation models used be as accurate as possible. Apanovich et al. [7] report that the coupling between non-local charge transport and nonisothermal effects are significant in SOI devices on account of the low thermal conductivity of the buried oxide and the parasitic bipolar effect. Non-isothermal models were found to predict impact ionization and secondary breakdown more accurately than isothermal models, thus highlighting the influence of lattice heating on the electrical behavior of devices. Wachutka [8] describes the source of nonisothermal effects in electronic devices in great detail. The Wachutka model for device thermal characterization accounts for non-equilibrium phenomena such as generation-recombination, Joule and Thomson heating. The model is also valid for transient simulations where the difference in thermal behavior of the two modes of lattice vibrations, the optical and acoustic phonons, is most pronounced. It is this difference between phonons that is responsible for thermal non-equilibrium in the active region of the device. Lai and Majumdar [9] have developed a coupled electrothermal model for studying non-equilibrium in sub-micron silicon MOSFETs. They have determined the highest electron and lattice temperatures to be under the drain side of the gate electrode, which also corresponds to the region of highest electric field, and in turn the region where nonequilibrium effects such as impact ionization and velocity overshoot are maximum. Majumdar et al [10] have analyzed the variation of hot electron and associated hot phonon effects in GaAs MESFETs. These hot carrier effects were observed to decrease the output drain current by as much as 15%. Thus, they conclude that both electron and lattice heating must be included in the analysis of electrical behavior of a device. An important structural modification that has been suggested to overcome some of the inherent deficiencies of bulk Si LDMOS and SOI, is the partial SOI device. Bulk Si LDMOS, though they possess excellent thermal conduction properties, often suffer from large leakage currents. SOI devices were developed to isolate electrical activity. The buried oxide layer in these devices acts as an electrical insulator that minimizes leakage currents. However the oxide layer also acts as a barrier to thermal dissipation. This spatial confinement of local heating adversely affects the electrical performance of the device, as demonstrated by the literature cited above. In contrast to SOI, the buried oxide layer in partial SOI does not extend across the entire length of the device. Instead, a ‘silicon window’ under the drain region provides an efficient path for heat to diffuse away from the electrically active region. Figure 1 shows cross-sectional views of these LDMOS devices.